This invention relates to buffer or latch circuitry, and more particular to a CMOS circuit for use as an address buffer in a semiconductor dynamic read/write memory device.
Bistable latch circuits are used as differential detectors for the address inputs in dynamic RAM devices. An address input terminal of such a device is gated into one input of the bistable circuit, and a reference voltage is applied to the other input. The reference is chosen to be midway between a maximum TTL level zero and a minimum TTL level one. Examples of circuits of this type are shown in U.S. Pat. No. 4,280,070, issued to Reese, White and McAlexander, U.S. Pat. No. 4,031,415, issued to Redwine and Kitagawa, and U.S. Pat. No. 4,110,639, issued to Redwine, all assigned to Texas Instruments.
As the bit density in DRAMs has increased to 256K-bit and 1-Megabit levels, and as the functional specifications of such devices have been made more stringent in timing and broadened to include more addressing modes, the address buffers are required to operate faster and use less power; of course the complexity of the clocking needed should always be minimized.
It is the principal object of this invention to provide an improved address buffer circuit for a semiconductor memory or the like. Another object is to provide a latch circuit of low power consumption, of high speed, of simple construction, and/or with minimum complexity in clocking.